The invention relates to a process for planarizing a nonplanar surface and, more particularly, to a process for forming a planarized multilevel chip wiring structure.
A semiconductor chip consists of an array of semiconductor devices whose contacts are interconnected by metal patterns. The metal patterns, or nets, are sometimes multi-layered and separated by an insulating material, like quartz. The thickness of the insulator is made sufficiently large to minimize capacitance between the different levels of wiring and also to render the insulator more tolerant to particulate defects. Connections between nets are made by via studs (also known as vertical wires) which penetrate the insulator. The vertical wire is formed by metal lift-off process described, for example, in U.S. Pat. No. 4,004,044 issued to Franco et al and assigned to the present assignee. The vertical wire is put in place before the insulator is deposited. Using reactive ion etching (RIE) or ion milling, the surface of the insulator is planarized and the top of the stud is exposed. Planarization is necessary since it improves the reliability of subsequent wiring levels as these wires do not have to traverse topography.
The prior art has attempted to planarize the insulator. In one approach, described in IBM Technical Disclosure Bulletin, Vol. 23, No. 9, p. 4140, Feb. 1981 entitled "Dual Dielectric For Multilevel Metal", after forming the metallization pattern in a substrate, planar quartz of a thickness equal to the metal thickness is deposited, and coated with a planarizing resist layer. The resist and quartz are etched back to expose the surface of the metal lines. Vertical wiring is then formed on the metal lines, after incorporating a silicon nitride insulator, by lift-off process. Finally, a second layer of quartz or polyimide is deposited, planarized, and etched back to expose the studs.
U.S. Pat. No. 4,541,169 issued to Bartush and assigned to the present assignee discloses a planarization process in the context of making studs at different levels in a chip. After forming the metal studs on first level metal wiring, silicon dioxide layer is deposited and planarized, by etching using a thick photoresist planarization layer, to expose the most elevated studs. A silicon nitride layer is then deposited and using the same mask pattern used to delineate the studs, the nitride (and the residual oxide over the the depressed studs) is etched to expose all the studs.
U.S. Pat. No. 4,541,168 issued to Galie et al and assigned to the present assignee discloses a method for making metal contact studs between first level metal and regions of a semiconductor device with the studs butting against polyimide-filled trenches. The metal studs are formed by lift-off followed by sputter depositing silicon dioxide layer of thickness about the stud height, obtaining a nonplanar oxide structure. A planarizing photoresist is applied and the resist and oxide are etched to expose the studs.
A basic problem with these prior art methods is peak inversion. To explain, reference is made to FIGS. 1 and 2 wherein a semiconductor substrate 10 having two metal studs 12 and 14 of different width is illustrated. When an insulator, such as oxide, layer 16 is deposited over the studed structure, peaks 18 and mesas 20 of oxide will be formed over the narrow and wide studs 12 and 14, respectively. Upon applying a planarizing resist layer 22 and etching to expose the studs, due to the higher etch rate of oxide relative to the resist (etch rate ratio of quartz to resist is, typically, about 1.4:1.0), once the oxide peaks and mesas are exposed, these oxide structures tend to etch off more quickly than the remainder of the oxide (which is still protected by the resist 22 thereover). As a result, the peaks and mesas of the oxide are inverted as illustrated in FIG. 2. The resulting structure will be of nonplanar topography consisting of an oxide medium 16 having studs 12 and 14 and vias 24 and 26. Such topography is undesirable as it leads to breakage of the next level wiring metal that is subsequently formed owing to the steepness of the vias in the oxide. Also, the wiring is prone to be fractured due to the sharp edges of the studs, leading to a low device yield and/or reliability. Yet another problem is poor step coverage at the edges of the studs, which, due to electromigration, poses reliability concerns. Thus, it is imperative to obtain a planar surface to have high device yield and reliability.
It would appear that one way of avoiding peak inversion is to obtain 1:1 etch rate ratio of the oxide to photoresist by drying or heating the photoresist as disclosed in U.S. Pat. No. 4,025,411 issued to Hom-Ma et al. However, solidification of the resist by heat treatment does not, in practice, render the etch rate of resist fully compatible with that of the interlevel insulator, particularly when the insulator is other than oxide. Another attempted solution to the above etch rate disparity between resist and oxide is to select the etching conditions (of RIE or ion milling), etchant systems, etc., which would obtain a 1:1 etch rate ratio. However, the process window which would provide such 1:1 etch rate ratio is extremely limited and difficult to control, rendering this approach unsuitable for a high volume manufacturing environment.
Accordingly, it is the principal object of the invention to provide a process by which the etch rate ratio of interlevel insulator material to the planarizing medium is consistently and reliably rendered 1:1.